Timing error becomes measurement error
An ADC samples at clock-defined instants. Small variations, called jitter, change the sampled value; a steep input waveform is especially sensitive.
Evaluate the whole chain
Consider the source, distribution, power and board environment together. Clock quality at the converter matters more than an isolated oscillator specification.
A repeatable test plan
- Record input frequency and measurement conditions
- Compare against an appropriate reference clock
- Check noise while digital sections are active
- Record settings, cables and measurement bandwidth
Derive the jitter requirement from the application and converter, rather than applying one target to every project.